Design And Implementation Of The Modulator In National DTTB Standard

This dissertation focuses on the hardware implementation of the modulator in national DTTB(Digital Television Terrestrial Broadcasting) standard, and it presents a hardware implementation scheme which supports all the modes in DTTB standard with low complexity. We introduce an efficient encoding algorithm with shift register adder accumulator circuit based on the research of LDPC(Low-density Parity-check) coding. The scheme we present and implement can reduce about 40% of the logic cells in FPGA(Field Programmable Gate Array) due to the new method which can share the hardware resource in different LDPC encoding rates.We propose a hardware implementation structure for 3780-point FFT which has high precision and low complexity after traversing the FFT algorithms. By analysis of error and fix-point simulation, the algorithm is optimized and the length of byte is ascertained. By making use of the signal structure in DTTB standard skillfully, we reduce the use of RAM by 44% and implement the 3780-point IFFT in FPGA with the output SNR up to 61dB.Finally, we design and implement the hardware platform, considering the purpose and function of the modulator. The methods of debugging the programme and hardware platform are presented and the problems encountered and their solving methods are also included.