Digital Television Terrestrial Broadcasting Transmission System Ldpc Codec Program Design

Low density parity check(LDPC)code is proposed in 1962 by Gallager, which is one kind of the near Shannon Limitation error correction code. In order to achieve better performance, the random sparse parity check matrix is generally used in the LDPC researches. But the random architecture of check matrix leads to huge resource requirement for LDPC hardware implementation. The quasi-cyclic (QC-LDPC) is one of practical solutions for this issue.This thesis aims at the characters of QC-LDPC codes used in the digital terrestrial television broadcasting system, researches encoding and decoding algorithm:In encoding, based on the traditional algorithm, a method to reduce the complexity of QC-LDPC codes for the encoder circuit design and implementation is used. Three typical encoding circuits by registers of feedback-shift and logic gates are designed: Serial input QC-LDPC encoder based on SRAA circuit; Parallel input QC-LDPC encoder based on SRAA circuit; Two-stage encode circuit. According to the requirement of QC-LDPC codes system use, a multi-rate QC-LDPC encoder is designed. Encoder is made by four function modules: input cache unit, generate matrix storage unit, matrix multiplication unit and output cache unit. By selecting the pins, implement a triple rate encoder suitable for DMB-T system. This encoder supports three encoding pattern: rate0.4, rate0.6 and rate 0.8.By the implement of Altera's FPGA on this encoder, it only occupies 5,486 LE units at FPGA logic elements of 7%, costs 432,406 bits memory resource at whole memory elements of 6%.In decoding, several decoding algorithm has been analyzed and their performance have been comprised. It is advised that adapted decoding algorithm should be chose according to how the real system claim the performance and how much hardware resources. Algorithm which has been implemented on QC-LDPC decoder includes: general structural design, each computation units and semi-parallel structure. This algorithm is universal to all QC-LDPC codes. Finally, due to LDPC parity matrix, a special structure of decoder has been designed. And an efficient decoder multiplexing 3 code rates has been proposed and implemented. The simulation indicated: this triple decoder can not only maintains good performance of three rates, but also adds fewer resource cost compare with the single decoder.