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Research And FPGA Implementation Of LDPC Codes Decoder For Digital Television Broadcasting System

Posted on:2009-03-14Degree:MasterType:Thesis
Country:ChinaCandidate:C R LuFull Text:PDF
GTID:2178360242989292Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Low-density parity-check(LDPC)codes are excellent error-correcting codes with performance close to the Shannon limit.It is adapted for hardware's hight speed implementation because of its low decoding complexity.It also has better flexibility and lower error floor.LDPC codes is one of the key technologies in the 4G mobile communication.It is widely applied in many fields,such as fixed and wireless communication,satellite communication,digital television and broadcasting,optical fiber communication,and magnetic recorders,etc.Among these fields,digital television is an industry which gets lots of attention and is developing in a high speed.The development of digital television will be great significance for the whole electronic information industry.LDPC codes had been chosen to be a part of the channel coding scheme in many digital television broadcasting system standards,such as the Digital Television Terrestrial Broadcasting System standard DMB-TH,the Mobile Multimedia Broadcasting industry standard CMMB and the European standard Digital Video Broadcasting Second generation DVB-S2,etc.With the FEC coding technology LDPC codes,these standards can make their systems more reliable and do more wireless multimedia services.In this paper,based on the standards of the three digital television broadcasting systems,DMB-TH,CMMB and DVB-S2,a deep research about the channel coding LDPC codes is finished,and the decoders of LDPC codes are implemented by FPGA.First,the decoding methods of LDPC codes are summarized,and several typical decoding algorithms are compared and analyzed.Then the characteristics of LDPC codes used in the standards are researched and the parameters selection of decoding method is done by the performance simulaition.Next,with the characteristics and the parameters,the decoder of the LDPC codes are designed and implemented on the FPGA platform.At last,using VB and MATLAB,a special kind of software-hardware testing platform applicable for LDPC codes encoding and decoding test system is designed and built.And finally,the performance of the LDPC decoder is tested and verified.
Keywords/Search Tags:LDPC codes, decoder, Digital Television, FPGA, DMB-TH, CMMB, DVB-S2
PDF Full Text Request
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