Research And Implementation Of Concatenated Code About China Digital Television Multimedia Broadcasting

Forward Error Correction code (FEC) is widely used in modern communication systems, as it has several advantages such as easily encoding, strong ability to correct errors and avoiding the influence from channel noise. Conventional communication systems only utilizes forward error correction code technique, it is obviously insufficient in the error correction capability and has other disadvantages. In order to approach the maximum channel capacity and decrease the bit error rate, the method of concatenated code was adopted. Low Density Parity Check(LDPC) code concatenated BCH code is utilized by China Digital Television Multimedia Broadcasting System (DTMB) to correct errors. This paper studied the performance of concatenated LDPC and BCH code and carried out its implementation. The major work of this paper is as follows:1. The performance of the concatenated code is simulated by Matlab with the help of interleave technique. The result shows that BCH code can effectively clear error floor induced by LDPC decoder at bit error rate of 10-6, and the coding gain can rise 0.3dB. After adding interleaver, the coding gain of concatenated decoder can increase 0.1 dB at bit error rate of 10-4.2. By improving the multiplier in Galois Field, the combinational logic delay and the load of the single gate circuit are decreased. BCH parallel encoder coincided with DTMB is designed to decrease the cost of clock and reduces the influence of fanout bottleneck. The encoder can encode consecutive bitstreams and fulfill the sequence requirement in the standard.3. Syndrome circuit is improved to decrease the number of multiplier and adder to only one. The parallel Chien search circuit which is designed by using single constant input multiplier has low cost in hardware, and the circuit is adjusted to fit for short BCH code. The structure of BCH decoder with two-stage pipeline is proposed. The decoder needs only 96 clocks to decode one code. The synthesis result from Altera QuartusⅡshows that the max operating frequency of the decoder can achieve 256.94MHz.4. The USB interface circuit based on chip.PDIUSBD12 is designed, together with PC software and daughterboard of USB interface. Test results show that the transmit speed of the interface is up to 200KBps.5. The test platform is built and the module of bit changing and FIFO is also designed to meet the data requirement of DTMB decoder. The performance of concatenated decoder was verified in the FPGA of Xilinx Virtex-4. The hardware test shows identical results with the simulation on software. This work shows good value in the realization of DTMB standard algorithm, andcan be extended to applications in related fields.This dissertation work is supported by Foundation of Shanghai Science and Technology Committee under project "Research on high-performance ASIP architecture based on LDPC" (No. 08700741200), open project of Key Lab of Wireless Sensor Network & Communication, Chinese Academy of Sciences "Research on ASIP architecture based on LDPC in wireless communications"...