Digital Watermarking Technology Based On LDPC Code And Chaotic Sequence

People can get all kinds of information from the Internet with the advancement of information technology.However,while information technology brings benefits to people,security of information such as illegal copying and counterfeiting also follow.The protection of intellectual property rights has become a current focus of research,and digital watermarking technology is an effective means to solve copyright disputes.In recent years,many researchers have introduced error control coding into digital watermarking technology,which has improved the robustness of digital watermarking better.LDPC code,as a research hotspot in recent years,has been studied extensively in digital watermarkingIn this thesis,the application of LDPC code and chaotic sequence in digital watermarking system is studied by combining theoretical analysis and experimental simulation.The main work of this thesis is as follows:(1)Aiming at the characteristics of digital watermarking technology with low demand for immediacy,in this thesis,the existing LDPC code belief propagation decoding algorithm was improved,and the oscillation iteration problem in belief propagation decoding algorithm of LDPC codes is analyzed.To reduce the disadvantageous effect of oscillation effect on decoding and improve the reliability of decoding algorithm,a part of computation is added.In this thesis,the digital watermark is encoded by LDPC,and then the encoded watermark information is double encrypted by the multi-chaotic system to further improve the security of the digital watermark.(2)The embedding and extracting algorithms of common digital watermarks are simulated,and the improved decoding algorithm and multi-chaos encryption system are introduced into the digital watermarking system.Finally,the simulation implementation and performance analysis of the improved digital watermarking system are carried out by using MATLAB.(3)FPGA is used to design the hardware of the improved LDPC decoding algorithm,Verilog HDL is used to realize the FPGA design of LDPC decoder.In order to prove the feasibility of the design,the time series simulation diagram given by Modelsim.(4)Finally,the research work of this thesis is summarized and the future research direction is prospected.