Digital Image Information Hiding Algorithm Research Based On LDPC Code

LDPC code is a parity check code,its performance is very closed to Shannon limit,it is a sort of good channel code.The coding can be introduced to information hiding algorithm because of its functional advantages,such as error correcting capability.This way can improve robustness of system of information in the process of hiding,and it has good application prospect.Information hiding is based on encrypting important information to realize the security of transmission.The traditional information hiding algorithm in terms of confidentiality and anti-jamming is poorer.In this paper chaotic sequence scrambling and LDPC codes are proposed.Firstly,to implement scrambling encryption,after use LDPC coding and modulation,and then embedded into the carrier image,the watermark extraction is through the scrambling and decoding process.The method realizes the double encryption of information,and improves the system stability and security.Under the test of MATLAB software and FPGA hardware emulation,the superior application of LDPC code in information hiding algorithm is fully verified.In summary,the arrangements of the paper are divided into the following aspects:Firstly,starting from the background of digital communication,the paper introduces the status of channel coding,it focuses on the basic concept and description of LDPC codes,the construction method of coding,various coding algorithms and the corresponding algorithms of decoding.This content lays a good foundation for LDPC to apply for digital watermarking.Secondly,the concept and application of information hiding algorithm are introduced in detail,mainly including digital watermarking algorithm applying LDPC code and chaos encryption algorithm.Finally,it is proposed to combine LDPC code and chaotic sequence applied to digital watermarking to realize double encryption.Through the MATLAB simulation and a variety of attack algorithm test,the algorithm can be proved has superiority.Thirdly,LDPC decoder is designed in FPGA hardware.The hardware module is programmed and designed though the use of hardware language Verilog.We can observe the simulation diagram by the implementation of Modelsim.The design verifies the correctness of LDPC Decoder in Watermark Extraction Algorithm.Finally,summarize the research work done in this paper,correct deficiencies,and look forward to future work.