Rs Decoder And The Ldpc Codec Design And Hardware Implementation Of Digital Television

The channel code system is one of the most significant components in digital communication systems. The FEC of channel codes can enhance reliability of messages-transforming without breaking real-time constraint of communication systems. With the development of the coding theory and VLSI technology, lots of FECs,which were hard to implement before, can be gradually implemented in communication systems. Designing FEC systems by VLSI technology, which can meet the requst of reliability and real-time in communication while obtaining high-speed and low-overhead in integrated circuit, is an important component in designing communication systems.Based on the research of RS code and LDPC code, the architecture design and the hardware implementation are presented in this paper. The mainly contents of the paper are as follows:(1) Design and implenmention of a RS decoder with the iBM algorithm.(2) Design and optimization of GF multiplier.(3) Design and implenmention of a LDPC encoder and a LDPC decoder.(4) A new LDPC encoder construction is proposed, which utilizes the quasi-cyclic features of G matrix to achieve high implement efficiency.(5) A new architecture based on stacks of BCJR-decoding module is proposed.(6) A new architecture based on cyclic-offset of programmable interleaver is proposed for the LDPC decoder.