The Design Of A 12-bit Medium-speed DAC

The purpose of this project is to realize a design of a 12-bit medium-speed digital-to-analog converter (DAC), the design target is to reach 40K/Hz, INL<±1/2LSB, DNL<1LSB.With the fast development of computer technology, multimedia technology, digital processing technology and microelectronics technology, advanced electronic systems are presented continuously. DACs are applied to both front-end and back-end of modern advanced electronic systems. In recent years, DACs'market has shown a developing trend with stable growth, DACs also have played an important role in the modern army and civil electronic systems.According to the designing requirement, after comparing with many structures of DAC, the voltage-mode R-2R ladder network DAC is decided, as it's structure is relatively simple, resulting in lower difficulty for designing. The input mode is serial-input, which meets the requirement of medium-speed; and the output mode is voltage-mode ,which could satisfy the demand of mass application.The DAC consists of analog circuits blocks(R-2R ladder network and output buffered operational amplifier) and digital circuit blocks(Control Logic circuit, Serial-Shift-Register and DAC Register), so it's a mixed signal circuit. The design-flow is adopted as follow: It's to draw schematic and custom layout manually, edit the DRC, extract the components and parasitical parameters of layout, edit the LVS, and finish the post-simulation verification.The chip is fabricated on the 0.6-μm BiCMOS process (twin well, double poly and double metal) of XFAB. The chip area is 1.2×1.3=1.56 mm~2.According to the simulation results, the INL and DNL of the DAC chip are 0.8LSB and 0.5LSB respectively, and the settling time is 16μs.