Interface Design Of Video Decoding System Based On FPGA

This Video decoding system is to provide a based on FPGA test platform for video decoding chip design, and a good interface controller design for the application of the chip. The based on FPGA interface controller design can greatly reduce the development time and related costs of the system.The hardware of system is mainly composed of FPGA module, PCI interface module, SDRAM module and output module. When a large number of video coding data flow transmit to the system board using PCI bus interface of PC, the flow of TS code then will be decode in FPGA module, the final processing video signals will be output to the TV through output interface. FPGA module for the entire process includes video decryption, PCI interface controller, SDRAM interface controller and output interface controller these four major functions. The system uses Xilinx Virtex-II series FPGA devices to implement functional design, uses Micron companies SDRAM as external memory. Through the design of the interface controller, video decryption certification chips can achieve the AVS standards with real-time Standard Definition and 10 frames per second for High-Definition, and H.264 standard with 23 frames per second for Standard Definition and 5 frames per second for High-Definition.Besides the description of the hardware design of the whole system, the thesis also contains some certification of High-speed PCB board design. Furthermore, there are some presentations about the usage of FPGA design flow. Through FPGA design method, take interface controller as an example, the detailed account of the PCI bus interface controller and SDRAM interface controller are give out. As for theoretical foundation, there are also some introduction of PCI bus and SDRAM interface standard in the thesis.The research of video decryption certification system will provide hardware certification environment for digital video chip, and it can be used as a complete demonstration platform for users.