| High frame rate,high resolution,and high density are the current development direction of Light Detection and Ranging(LiDAR)array detectors.However,with the increase of the data volume of detector arrays and the limitation of the I/O interface transmission rate,traditional data transmission interfaces can no longer meet the development requirements of high-performance array detectors.Therefore,this thesis proposes a Low Voltage Differential Signaling(LVDS)interface transmitter circuit with low power consumption,low electromagnetic interference,and strong anti-noise performance to achieve high-speed and high-quality transmission of LiDAR array detector data.The main research contents of this thesis are as follows:(1)Based on the application requirements of LiDAR array detectors and the ANSI/TIA/EIA-644 A protocol standard,a high-speed LVDS transmitter circuit is studied and designed.A reliable commonmode feedback circuit and bandgap reference source are proposed to suppress the offset of the output DC operating point.An adjustable pre-emphasis circuit is designed to dynamically compensate for the high-frequency component attenuation of the output.A pre-drive circuit based on a fulldifferential topology design is introduced to control the output voltage swing,reduce impedance mismatch effects,and suppress ringing.An embedded clock SerDes(Serializer/Deserializer)architecture is adopted to improve interconnect flexibility and make the receiver easier to complete deserialization operations.The circuit and layout design is completed based on the 180-nm CMOS process.The post-simulation results show that the interface transmission rate can reach 1 Gbps,the output common-mode voltage level under various process corners is maintained at around 1.25 V,the maximum offset is less than 72 m V,the differential output voltage is maintained between 362 m V and 426 m V,the rise/fall time of the differential output signal is 445 ps～531 ps,the output data eye diagram width is greater than 0.976UI(Unit Interval),and the eye diagram jitter is less than 0.024 UI,meeting protocol requirements.In addition,the Monte Carlo post-simulation results of the designed low-voltage gap reference source show that its mean value is 694 m V,and the temperature coefficient within the wide temperature range of-40 ℃ to 140 ℃ is only 0.78 ppm/℃.(2)To meet the clock requirements of the serializer in the LVDS transmitter and the clock synchronization problem between the transmitter and receiver,combined with the transmission rate requirements of LiDAR array detectors,a low-jitter Phase-Locked Loop(PLL)circuit is studied,and designed.Based on the analysis of the basic principles and sampling characteristics of PLL,an Sdomain loop model is established,the parameter initial values are determined according to the design requirements,the initial value verification is completed by building a Simulink behavioral-level model,and the loop parameters are optimized using noise analysis.For the design of the circuit module to achieve low-jitter design requirements,a latch architecture is introduced in the output link of the non-dead-zone phase/frequency detector to optimize signal synchronization.The source follower charge pump and rail-to-rail op-amp application can obtain lower in-band noise contribution within a wider output range.Using a differential ring voltage-controlled oscillator to save area,and using auxiliary tuning to achieve lower out-of-band noise while broadening the frequency tuning range.A second-order loop filter is used to stabilize the PLL loop,filter out high-frequency noise,and suppress the occurrence of spurious noise.After completion of the circuit simulation verification under various process corners,the results show that the output frequency range is 400 MHz to 1 GHz.At an output frequency of 800 MHz,the control voltage ripple is less than 1.86 m V,the frequency jitter is less than 811 KHz,the period jitter is less than 1.26 ps,the peak-to-peak jitter is less than 2.96 ps,and the duty cycle is greater than 49.35%. |
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