The Functional Verification Of Digital IC: Research Of Modeling Language,Stimulus-Generation And Instances

With the rapid growth of scale of integrated circuit,the complexity of integrated circuit's function increases as well.On one hand,it has brought vigor and vitality to information technology.On the other hand,it causes many problems and challenges.The functional correctness of integrated circuit is the key factor among them,so we must pay enough attention to it.In traditional functional verification work,the test vector is written by validation engineers manually.This way of verification may cause inefficient verification result.With the development of technology,some advanced verification methods are introduced successfully to enrich the library of validation technology,such as OVM and UVM.But these validation methods are based on signal or transaction level mainly,not from a higher level of function-point to consider validation issues,and the generalization and decomposition of function-point still exists some deficiencies.Besides,the test vectors still need to be encapsulated artificially,which increases the difficulty of building verification platform to some extent.To make up the deficiency of verification technology in function-modeling and generating stimulation automatically,and explore new validation mothods from different aspects,our research team carried out corresponding research.The research work and progress on technology include the following several points in this paper.1.Our research team construct a hierarchical function model F-M for each functionpoint based on functional characteristics of IC,analysis of functional specification and the demand of function verification work.Our research group has developed a functionmodel description language of functional specification according to the function model F-M,and define the expression rule to describe the functional behavior of modules as digital system and IP core.2.Using C/C++ to construct a parse-compiler P-C to parse the function model language,and build the stimulus-generator and assertion-detector automatically.Then build the verification platform based on SystemVerilog,and generate the stimulus automatically.3.We take FT_X_DMA slave-part as an example,and use our verification method and UVM method to finish the validation work respectively.Then we compare these two methods from function-modeling,stimulation-generating and combining and verification efficiency,etc.Then we analysis the differences between different validation methods.The experimental results show that,the differentia between the two verification methods includes several points below.First,we construct the function model based on functional specification.Second,stimulation can be generated automatically,which saves a large of manpower.Third,the difficulty of building the verification platform is lower than tranditional verification methods.As an exploratory subject,the work of this paper enriched the validation library to some extent,and made efforts to explore new methods of validation.But we can see that our work still has lots of room to improve,such as the normative integrity of function model description language,the completeness of verification platform structure,etc.We still need to pay more effort to ameliorate them.