The Application Research Of System Verilog Assertion-Based Functional Verification

Functional verification has become the biggest bottleneck in Modern IC design process. The deficiencies of traditional verification method are as follows: poor observability and controllability in verify process, finding bugs effectivelessly, more verification cycle and lower reusability of verification environment, which restrict the verification efficiency. So we introduce the Assertion-Based Verification to improve our work method. ABV makes up the dynamic simulation deficiencies effectively with assertion advantages.The main purpose of this dissertation is to introduce the SVA-Based functional verification method in the application of actual project. We expound the ABV method and ABV flow at the beginning, and make a detail introduction of SVA(SystemVerilog Assertion) which is one of the assertion languages. In Dual interface card project, we use ABV method based on SVA and constraint-random platform which is built based on VMM together to debug the RF interface controller module. The process of extract design property and build SVA checkers is introduced in details, we developed an ISO/IEC14443 protocol interface checker and other corresponding monitors during the verification work. Finally, we make a record and a brief interpretation of the verification results.The SVA checkers developed in this dissertation are successfully applied in the actual project, especially the ISO/IEC14443 protocol assertion checker has been used in several contactless-card verification works. The experimental results show that, the Assertion-Based Verification can improve the observability and controllability, find the design bugs effectively, reduce the amount of time spent debugging problems, improve verification quality, and increase the confidence of designer.