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Finite Element Analysis Of TSOP Failure During Mould Release And Temperature Distribution In Polysilicon TFT Under Self-heating Stress

Posted on:2008-07-07Degree:MasterType:Thesis
Country:ChinaCandidate:Z Y YangFull Text:PDF
GTID:2178360218450928Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
In this thesis, molding process for a typical TSOP product is studied in detail, and FEA(Finite element analysis) has been applied in this process.During molding process, silicon die crack failures might occur in some types of thin small outline package (TSOP) at mould release step. This step is simulated by finite element method to clarify the mechanism of silicon die crack failures. It is demonstrated that some adhesion area by organic contamination on mould inner surface, may impede package block from being smoothly released from the mould, leading to locally built high internal stress within silicon and causing die crack. Die crack risks with adhesion area in different sizes, shapes and positions are compared. High-risk conditions are defined. Die crack failure can be reduced by using high elastic molding compound, and is also reduced in small silicon die package. Our study would be beneficial to improve the reliability of TSOP products.The temperature distribution of the typical-sized n-type metal induced lateral crystallized polycrystalline silicon thin film transistors under self-heating stress is also simulated. The influence of the power density, substrate material characteristic and channel width to the temperature distribution were investigated by FEA. Reduction of the power density can decrease the heat generation on area directly and lower the channel temperature. And under the same power density, the increase of the channel width will increase the heating area and so minish the width is important to reduce the channel temperature. Improve the thermal conductivity of substrate material can transfer the heat through substrate better, or a small power density can induce a high temperature. Through the transient thermal analysis, we can get the device's characteristic coefficient on time. This coefficient can be reduced a lot with a substrate material having better thermal conductivity. Our study indicates that minish the power density, adopt the substrate with better thermal conductivity and decrease the channel width can lower the channel temperature. Our study would be helpful to undstand the mechanism of self-heating degradation and improve the reliability of TFT.
Keywords/Search Tags:FEA, die crack failure, molding, mould release, stress, thin film transistor, self-heating degradation, temperature distribution
PDF Full Text Request
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