Degradation Of Amorphous Silicon Thin Film Transistors Under Gate And Drain Voltage Bias Stress

Degradation of a-Si TFTs under different stress conditions has been systematically investigated. For positive gate bias (V_g) stress, state creation and/or electron trapping mechanism lead to the positive shift of the device threshold voltage (V_th). And the degradation follows asΔV t h =CV_gγt^β, whereγ≈1. 5,β≈0.34. For negative V_g stress, in DC stress, domination of state creation mechanism generally causes +V_th shift. While for AC stress, domination of state creation or hole trapping mechanism depends on stress frequency (f) and stress time. Besides, recovery phenomena related to both mechanisms are both observed. The leakage current decreases under low f V_g stress but increases under high f V_g stress.For drain bias (Vd) stress with fixed V_g, in DC stress, state creation dominates for relative large V_gd (V_gd =V_g Vd) while electron trapping dominates for +V_gd. While in AC stress, state creation, electron trapping and hole trapping contribute to the degradation. Dominant mechanism depends on stress time, f and polarity of V_gd.Output characterization induced device degradation has been found and investigated for n-type low temperature (LT) polysilicon TFTs. Degradation mechanism is found to be related to the DC hot carrier effect. Since a routine device output measurement can induce significant degradation in LT crystallized TFTs, pulse IV method is used to obtain an accurate output measurement without much affecting the device under test.