Degradation Of Thin Film Transistors Under Dynamic Bias Stresses

In recent years, the thin film transistors(TFTs) implemented poly-Si or metal oxide semiconductor as channel active layer have received considerable attraction in next generation flat-panel industry featured as new techlonogies such as high definition TV, smart or touchable multimedia technology and so on. Nowdays, TFT techlonogies based on low temperature poly-Si(LTPS) and amorphous InGa ZnO(a-IGZO) are two of the important research drirections for the next generation flat-panel scheme due to the TFTs holding higher mobility, low process and other advantages. However, the reliability issues of TFTs limit the further development of the flat-panel industry. Concerning practical working circuits, TFTs not only suffer from the DC bias but also the AC singal or pulse stresses switching between ON and OFF state. Generally speaking, the influence of DC biases and corresponding the physical degradation process has been clarified, however, up to now, there is no universal degradation model for explaining the degradation behaviors of TFTs when are biased under pulsed stresses. Thus, in this work, the degradation behaviors under dynamic stresses and its controlling mechanisms are systematically investigated, respectively. The main contents and results are summaried as following:(1) The degradation of LTPS TFTs under dynamic stressesAfter applying the pulse stress to gate electrode of LTPS TFTs, we investigated the device degradation in detail by changing the pulse parameters, such as pulse falling/rising time and pulse repetitions et al., and concluded that device degradation depends on pulse repetitions and takes place at pulse falling time. Then, as for the degradation mechanism, we proposal a non-equlibrium PN junction degradation model to explain the generation of hot carrier(HC) during the pulse falling time, in which the carriers trapped in defects are emitted via trap ionization and exposed in high electrical field near the soure/drain, forming the HCs. The degradation model can explain the degradation phenomena comprehensively.(2) The degradation suppression of new type TFT with carrier injection terminalAccording to our proposed model, we fabricated a new type TFT with carrier injection terminal to suppress the device degradation and improve the device lifetime. The structure is introduced to provide to the semiconductor channel region a carrier whose the polarity is reverse to that of a channel carrier in on-state of the TFT, then, eliminating non-equilibrium state depletion region of the two junctions. That is, during the pulse falling transition the channel being driven into the accumulation state, it can readily supply holes into channel region. As a result, the variation of carrier in channel can follow the switch of gate pulse as far as possible, and then, suppress the device degradation under dynamic stresses.(3) The dynamic degradation of a-IGZO TFTsFirst, the instability of a-IGZO TFT under typical gate pulse is investigated. By comparing the influence of pulse rising and falling time on dynamic degradation, we found that, if the pulse falling time is steeper, the dynamic degradation dependent on the pulse repetition can be attributed to the electron-trapping involved HCs effect, which is very similar to the dynamic degradation of LTPS TFT. On the contrary, if the falling time is gradual, DC effect controls the dynamic degradation which can be determined by effective stress time. Electron-trapping uniformly in the interface between channel and a-IGZO are the main reason while the dynamic affect of HCs can be ignored. Here, we proposed dynamic degradation mechanism for steeper falling time of gate pulse, in which electrons unable to return to source and drain are exposed in high lateral transient field and become HCs, then, parts of HCs could be trapped in infterface or injected into gate insulator after surmounting the the barrier of interface, resulting to characterization degradation. In addition, the model is further verified by Silvaco simulation.Different from the degaradation under gate pulses, the degradation caused by eithor synchronized gate/drain pulses or the drain pulses only is essentially resulted from the DC bias, both of them depends on the period time of high voltage level rather than the dynamic pulse transition. It is worthy to point out that the final quantitation of degradation not only depends on the equivalent DC stress but also influences by the pulse duty due to the recovery phenomena once removing the applied stress. We inferred that electrons injection and/or trapping are responsible for the degradation under the two tpyes pulse stresses and enhanced at elevated temperature.