Degradation Behaviors Of Metal Induced Lateral Crystallized N-type Polysilicon Thin Film Transistors Under DC Bias Stresses

Device degradation behaviors of typical-sized n-type metal induced lateral crystallized polycrystalline silicon thin film transistors were investigated under two kinds of DC bias stresses: hot carrier stress and self-heating stress. Degradation dependences and mechanisms were studied and discussed in details on different stress voltage and duration conditions. Under hot carrier stress, device degradation is the consequence of hot carrier induced defect generation locally at drain side. Under a unified model of carrier transport over trap state established potential barrier at drain side, device degradation behavior such as asymmetric on-current recovery and threshold voltage degradation can be understood. Under self-heating stress, a general degradation in subthreshold characteristic was observed, which is the consequence of defect generation along overall channel. Similar to hot carrier degradation, asymmetric on-current recovery was also observed and discussed. Device degradation behaviors are compared in low Vd-stress and in high Vd-stress condition. Defect generation distribution along the channel appears to be different in two cases. Several common degradation phenomena were also summarized from some recent typical research work on the reliability of low-temperature processed poly-silicon thin film transistors.