Investigation Of Device Degradation In N-Type Polycrystalline Silicon Thin Film Transistors Under Dynamic Voltage Stresses

This paper investigates device degradation behaviors and mechanisms in n-typepolycrystalline silicon (poly-Si) thin film transistors (TFTs) under dynamic voltage stress,including device degradation under synchronized gate and drain pulse stresses, devicedegradation under drain pulse stress with gate and source electrodes grounded and devicedegradation under fixed drain pulse stress with different gate DC bias.1) Device degradation under synchronized gate and drain pulse stressesON-state degradation is dominated by a pulse duty time related self-heating (SH)mechanism for low frequency stresses whereas by a pulse transient time related dynamichot carrier (HC) mechanism for high frequency stresses. OFF-state degradation isdominated by the dynamic HC effect, irrespective of stress frequency. It is first observedthat such dynamic HC degradation is independent of the pulse falling time (tf) butdependent on the rising time (tr). During tr, HCs are generated in the drain depletionregion by a high transient coupling electric field arising from Vg switching. However,during tf, the HC effect is screened by SH that causes high temperature rise. Devicesaturation is confirmed to play a key role in dynamic HC degradation under synchronizedstresses. The proposed degradation model is verified by comparing it with various stresstest results.2) Device degradation under drain pulse stressIt is first found that drain pulse stress can induce device degradation in n-type poly-SiTFTs. Through the analysis of transfer/output curve degradation behaviors, temperaturedependence experiment and device length dependence experiment, the degradation isconfirmed to be dominated by HC effect. Drain pulse induced dynamic HC degradationonly occurs under the certain pulse stress with high pulse amplitude and the degradation isdependent on tr but independent of tf. Faster tr brings larger device degradation. Based onthe experimental and simulation results, a non-equilibrium PN junction model takingcarrier emission/trapping into consideration is proposed to understand the degradatdegradation model is also verified by comparing it with various stress test results.3) Device degradation under fixed drain pulse stress with gate DC biasIt is first found that smaller DC Vg stress brings larger device degradation with fixeddrain pulse stress. For the positive DC Vg stress, two-stage degradation is observed. For the initial stage degradation, the DC effect may be responsible for it. While for the secondstage degradation, the tr related dynamic HC effect dominates the device degradation. Agood correspondence between on-state degradation and off-state degradation is alsoobtained. Based on the experimental and simulation results, the non-equilibrium PNjunction model is amended and developed.