Design And Research Of High-Speed CMOS Digital Imaging System

High-Speed Digital Imaging System provides a reliable testing technology and method to study the mechanism and laws of high-speed phenomena. It has been widely used in aviation, aerospace, enginery, nuclear technology and other fields.With the development of high-speed CMOS image sensor and CPLD/FPGA device, study of low-cost and high-speed digital imaging system has become possible. This dissertation studies the key technologies of the high-speed digital imaging system which based on LUPA1300 image sensor.According to the analyses result of the timing relation of the different modules in the system, the clock tree drive circuit was designed to meet the requirements of total system. In order to ensure the imaging signal has been sampled on correct moment, this circuit adjusts the skew of various synchronous clock signals accurately. After studied the timing relation of LUPA1300 image sensor, the driver logic circuit, integration time control logic circuit and variable multi-resolution image windowing timing logic circuit were designed by using Verilog HDL language and Top-Down method. All these circuit designs were programmed on the FPGA device. The high-speed multi-channel A/D convert circuit converts the analog image signal to digital, this circuit is consist of AD9288 device. The LVDS transmission circuit not only increases the distance transmitting high-speed digital image signal to Computer but also improves the reliability and the performance for anti-noises.By the design, testing and experiment, the high-speed CMOS digital imaging system has been completed. In 1280×1024 resolution, 414 frames per second can be achieved. By using programmable multi-resolution image windowing technology,the maximum 1,527 frames per second can be achieved. These provide a good foundation for developing the digital image system with independent intelligent property.