Design And Implementation Of The Timing Circuit For A High Performance And Wild Dynamic CMOS Image Sensor

This thesis is one part of the Crucial Science and Technology Project of Tianjin City: "Design of the CMOS Image Sensor with High Performance and Large Dynamic Range". CMOS image sensor has developed quickly due to its mature producing technics and research results of solid image sensor. It has become the key facility of image processing technology and been applied to a great many fields such as video camera, digital camera, mobile communication, safeguard, car airbag and fingerprint identification. The accomplishment of this project can settle a strong base to design other ASICs and implement system integration, and the products will have a wide market.The system design and implementing method of the controlling circuit of image sensor are discussed in the thesis. In allusion to the image sensor with dual-sampling pixel architecture, the timing functions of parallel exposure mode and roll exposure mode are detailedly narrated and analyzed, and an improved roll exposure mode is introduced. With this mode, the structure of pixel cell is simplified, the double sample storage is shared by one column, and the rate of collecting and processing images is improved. Following Top-Down IC design method, the design is divided into several sub-modules, and they are described in Verilog. Separate functional simulations, syntheses, and gate-level simulations of every sub-module are done at first before the whole system is synthesized and debugged.In the process of writing Verilog source codes, their synthesizability and reliability are considered at first. All the source codes are written in synthesizable Verilog sentences. Duel-clock control is applied to make design more reliable after synthesis. Key paths are optimized to minimize delays. The operating frequency can reach 117.95MHz after synthesized on Altera FPGA platform.