Studies On Asynchronous Multiplier Design And Implementation Techniques

Asynchronous integrated circuit generates the local clock signals of every pipeline stage using handshake protocol, instead of the global clock signal of its synchronous counterpartner. Because of its natural solution of such problems as clock skew and energy dissipation in traditional synchronous integrated circuits, and the average-case performance with perfect reusability and robustness it achieves, asynchronous integrated circuit design is becoming the research focus both at home and abroad.In this paper, the asynchronous integrated circuit design methodology based on macro cell is presented first, based on the analysis of traditional design methodologies. One of the main problems in asynchronous integrated circuit design is the lack of effective design methodology. Traditional asynchronous integrated circuit design uses full custom design with low efficiency, because the asynchronous circuit implementation needs novel circuit structures which do not exist in traditional standard cell library. The macro cell layout structure is compatible with the standard cell library. The new design methodology can automatically generate the macro cell layout from the full custom circuit structure, using the convenient EDA tools.Based on the new asynchronous integrated circuits design methodology, a 32-bit asynchronous multiplier is designed and implemented, which is composed of data path module, control path module and interface module. A 3-stage iteration pipeline structure and 4-2 compressor rows are adopted in the data path module, using 8-bit Booth decode algorithm. A redundant four-phase latch control (RFLC) protocol is presented and implemented in the control path, based on the analysis of various four-phase handshake protocols. For the sake of design simplification, delay matching strategy is used. The interface module uses a four-phase handshake protocol to communicate with periphery synchronous circuits. The layout of the asynchronous multiplier IP core is implemented in the HHNEC 0.35μm process, with the 4-2 compressor, carry propagation adder and control path in full custom novel circuit structure. The performance estimate and analysis of this multiplier are presented at last, which show that the asynchronous pipeline performance is appreciably lower than its synchronous counterpartner in full pipeline mode, while it gains a little performance advantage in non-pipeline mode.To sum up, an asynchronous integrated circuits design methodology based on macro cell and the corresponding design flow are introduced in this paper. A 32-bitasynchronous multiplier is implemented in this design flow. The performance estimate of this multiplier is presented at last.