Design And Realization Of A Mixed-Signal PLL In 0.13μm CMOS Process

PLL is one of the most important technologies for modern microprocessors. In the past thirty years, PLL has developed from Linear PLL to Digital PLL and Mixed-Signal PLL. Among the various PLLs, Charge-Pump PLL(CPPLL) has the widest pull-in range and the smallest zero capture phase error, and CPPLL has becoming the mainstream in recent years.To meet the need of a real project, a CPPLL in 0.13μm CMOS process has been developed, and it can be used as a hard IP in microprocessor and SOC design. To eliminate the popular overcharge of CPPLL, voltage track technology has been used. Low and High Frequency Detect circuits have been added to protect the PLL from dead-lock. Furthermore, shielding and layout techniques have been widely proposed to improve noise performance of the PLL.The main content includes:1. The fundamentals and most important mechanisms of PLL have been studied. The system model of PLL has been analyzed, and the stability of PLL loop has been lucubrated from both continuing and discrete-time characteristic.2. Noise sources and their impact on stability of PLL loop has been investigated, noise control methods have been proposed and used in real project.3. A power aware P&R(Placement And Routing) method has been proposed and realized in real PLL project.4. A high performance Mixed-signal PLL in 0.13μm CMOS process has been designed. The PLL has a wide frequency range from 200 to 800MHz.