Design Of The Key Functional Circuits For Single-chip UHF RFID Reader

Radio frequency identification technology is a technology, which can complete the identification of specific targets and reading or writing through the radio signals. Because of the unique performance, it is gradually applied in many fields. Based on the application requirements of ultra-high frequency RFID system, this paper designs and implements a kind of digital to analog convertors and low drop voltage regulators suitable for 860MHz~960MHz single-chip UHF RFID reader with CMOS,which has independent intellectual property rights. The research results in improving system performance and system flexibility has important value and broad application prospects. The research results are as follows:First of all, this paper designs and implements a segmented current-steering digitalanalog converter. The major part of the works includes analysis of the principles of digital-analog converter and common structures. Combined with the application requirements of UHF RFID, with the tool of MATLAB on section optimization. After considering the static parameters, dynamic parameters, area and power consumption, this design use of segmented "6+3+3" structure to implement. To further study the influence of various kinds of non-ideal factors on the performance of the error caused by the digitalanalog converter. These analysis and demonstration to guide the subsequent circuit design.Secondly, based on TSMC0.18 um CMOS process in Cadence design environment to achieve "6 +3+3" segmented current-steering DAC, including an analysis of the various components of the module, the design, layout drawing and simulation. Design modules include latch circuit, bandgap reference circuit, switch array, the array of current mirror and biasing circuit. The layout adopts "gong" to complete the wiring scheme and Q2 Random Walk for current source array. The integrated simulation results: 12 bits currentsteering DAC input sinusoidal signal at a frequency of 320 k Hz and sampling rate of 6.5MHz, the output amplitude of 500 m V. DNL=0.13 LSB, INL = 0.4LSB, SFDR=72.24 d B, effective number of bits is 12. The design can meet the criteria UHF RFID systems application requirements.The last part of this paper is about the UHF RFID Soc power management module. On the basis of research and analysis of the principles of system power management method, using TSMC 0.18 um CMOS process in Cadence environment designed to achieve three low-dropout linear regulator circuits. Complete system module design, layout design and simulation work. The simulation results show: the bandgap has low temperature coefficient is 6ppm/°C, designed and realized a gain of 58 d B, phase margin is 68.8 error amplifier circuit, completion temperature coefficient of less than 64ppm/°C, the conversion efficiency greater than 85% and accomplish specific customization UHF RFID reader module chip of LDO.In summary, this paper combines theoretical analysis with practical simulation, under the requirements of UHF RFID system, design and complete a high linearity and high dynamic range of segmented current steering digital to analog convertor circuit design, a low temperature drift high PSRR bandgap circuit and a group of low temperature drift and high linear adjustment rate low dropout linear regulator circuit design.