The Design Of C-S DAC Based On 0.18μm CMOS Technology

In response to growing market demand and reduce the domestic and foreign technical level gaps, This paper began on design of a high-speed (200MSPS) high- Resolution (14bit) C-S DAC, Completed for the following works:1, More weight in comparison binary encoding and the characteristics of the thermometer code, use the 5 +4 +5 hybrid coding to complete the 14-bit DAC design, Ensure accuracy in the case of small layout area, as far as possible to reduce costs.2, Fully grasp the thermometer code and binary code coding and decoding theory, we used method of making thermometer code output by the form of a unified method of expression to designed a decoder ,which not only com plete the decoding function ,but also ensure the consistency of the output signal timing. When designing Current source array, a new layout design idea ( center encircled) is put forward to reduce the high current source's matching error.3, Using the CFT from the mechanism of parasitic capacitance coupling, design a current switch drive signal generation circuit to reducing the output glitch, It does this by limiting the voltage drive signal voltage amplitude reduction to reduce the CFT effect; by reducing the drive signal's crossing point to avoid differential current switch open at the same time .4, Designed a low temperature coefficient bandgap voltage reference circuit to provide bias for entire DAC. Bandgap reference voltage connected to the input of an op amp to control the reference current generating circuit and current source array, that can usethe virtual Short and Virtual Open properties of op amp to reduce the impact of load on the reference voltage .5, Advantage of National Laboratory of Analog Integrated Circuits'technical platform, combined with 0.18μm CMOS process, completed the circuit design from the chip to verify the post-simulation design flow. The simulation shows that the overall circuit design of DAC chip DNL = 0.41LSB, INL = 0.68 LSB, Setting time = 1.7ns, when output signal is 97.46MHz, clock signal is 200M ,SFDR = 61.7dB; when output signal is 10MHz,clock signal 65M ,SFDR = 81.2dB; Pmax≦ 102mW. it's approached ADI's 14-bit DAC AD9744 overall performance , reached foreign countries' technological level of 2002.