Ldpc Codes Decoding Technology Research And Realization

Low Density Parity-Check (LDPC) Codes were first discovered by Gallager in the early 1960s and recently have been rediscovered and generalized. This class of codes decoded with soft-in soft-out (SISO) iterative decoding performs amazingly well. Since their rediscovery, design, construction, decoding, analysis and applications of LDPC coded have become focal points of research. Among them, the decoding algorithm and its implementation are the focus of this thesis.In this thesis, several iterative message passing algorithms for LDPC codes, such as Gallager's Bit Flipping (BF) algorithm, Weighted BF algorithm, Belief Propagation (BP) algorithm and normalized BP-Based algorithm etc, are considered. As one of contributions of this thesis, an improved decoding algorithm based on the WBF algorithm (WS-WBF) is proposed. Compared with WBF algorithm, it achieves considerable improvement with almost the same complexity. In order to break the infinite loop in the hard decision algorithm, a partial loop-break algorithm, which is much easier to implement, is also included in this thesis. At the same time, some key parameters and finite precision analysis for the hardware implementation of LDPC decoder have been performed considering the tradeoff between hardware complexity and error performance.Eventually, the architectures for the hardware implementation of LDPC decoder, including full parallel architecture, partly parallel architecture and serial architecture, have been analyzed. A method, which jointly conceiving code construction and decoder architecture, is introduced to approach the error performance of pseudorandom LDPC codes that exactly fit to high-speed partly parallel decoder and low-complexity encoder implementation. To demonstrate this joint design methodology, a FPGA implementation of 2304 1/2 regular LDPC code is realized using XilinxII6000 device. The design is described in the Verilog hardware description language (HDL) and SYNLIFY was used to synthesize the Verilog implementation. By performing maximum 10 decoding iterations, the decoder can achieve a maximum bit throughput of 50Mbps.