Optimization Of Decoding Algorithm And Decoder Design For Ldpc Codes

In the channel coding area, LDPC (Low-density parity-check) codes have a remarkable capacity-approaching performance with iterative decoding over AWGN (Additive White Gaussian Noise) channel, and have been adopted as the forward error correction technique by many high speed transmission technologies. This thesis focuses on the research and implementation of LDPC optimized decoding algorithm, our research result decreases hardware complexity in check node processing unit. The research concerns in this thesis are as follows:Firstly, this thesis introduces some basic knowledge of the channel coding theory, then traduces the LDPC code. This chapter begins with the definition of LDPC code, describes the presentation methods and the construction method of the LDPC codes.Secondly, we studied the decoding algorithm of LDPC codes, such as the BP algorithm and the LLR-BP algorithm. The BP algorithm and LLR-BP algorithm are difficult for hardware implementation because of their high complexities. Then, we introduce the Min-Sum decoding algorithm. The Min-Sum decoding algorithm is suboptimal, and naturally degrades the error-correcting performance compared with the BP algorithm. Therefore, the optimized Min-Sum decoding algorithm named Normalized Min-Sum algorithm and Offset Min-Sum algorithm are presented. The simulation results suggested that the Normalized Min-Sum algorithm is optimized for LDPC decoder.Next, in our thesis, to reduce the decoding complexity of Min-Sum decoding algorithm, we have to focus on the local simplification of the check node processing. In the Min-Sum decoding algorithm, the main task of the check node is to find the first minimum value and the second minimum value. The Tree Structure (TS) approach, which has low hardware cost, was developed to find the first minimum value and the second minimum value. To further reduce the hardware cost of check nodes, we propose the modified TS (MTS) approach.Then, in this thesis, we carried out the hardware implementation of the Normalized Min-Sum decoding algorithm based on the MTS approach. We use the idea of top-down designing and program with Verilog HDL. For comparing purpose, the structure block diagram was given and a decoding function module implementation method. Moreover, we synthesize and analyze the static time of the design with ISE14.3, Modelsim and Synplify Pro to verify the correctness. The simulation results show the precept of using FPGA to be the platform the hardware implementation is feasible. A576bits rate1/2LDPC codes of IEEE802.16e decoder is implemented on Nexys3Spartan-6FPGA XC6SLX16.