The Design Of RA Codes Encoder And Decoder Based On FPGA

The use of error correction coding technology to improve the reliability of information transmitted has become the research topic in the field of computer and communication.At present,LDPC code and Turbo code are two kinds error correction codes with the excellent performance of closing to the Shannon limit.RA code,which is a kind of Turbo code and LDPC code,has the advantages of linear time encoding of Turbo code and linear time decoding of LDPC code,and has certain practical value.The paper's main work includes: deducing encoding principle and decoding algorithm of RA code.Firstly,this paper introduces the concept and study domestic and overseas of RA code,including the representation of RA code.Secondly,this paper deduces the encoding principle and decoding algorithm of RA code.RA code adopts the encoding structure of Turbo code,and the interleaver directly affects the performance of the system.In this paper,the principle of block interleaver and random interleaver is introduced in detail.On this basis,the block interleaver is optimized to get the parity block interleaver,which overcomes the incompleteness of the decorrelation of the block interleaver and avoids the problem of large random numbers in the random interleaver.Then the message update rules of belief propagation decoding algorithm are deduced in white gaussian noise channel,and the simplified log likelihood ratio decoding algorithm and mini-sum decoding algorithm based on BP decoding algorithm are derived.The decoding performance in the Matlab is analyzed based on different decoding algorithms,different interleaving algorithms,different iterations and different normalized factors,and the hardware implementation parameters are determined.Finally,the paper chooses the Altera's DE2-70 development board as a hardware development platform,and uses Verilog language to write function code.The FPGA design of the RA code encoder mainly includes a repeater module,an interleaver module,a combiner module,and an accumulator module.According to the mini-sum decoding algorithm,the decoder is designed in semi-parallel structure,that is,the update of variable nodes and check nodes is carried out in parallel and in-block serial mode.This scheme effectively reduces the complexity of the decoding circuit.