The Research And Design Of Digital TV Channel Coding System

In recent years the design of DTV equipment has been a hotspot and the development of IP core with self-owned intellectual property is the most important. Designing an efficient encoder is very important to the overall performance and anti-interference ability of the whole DTV system. The paper proposes the channel coding scheme based on European DVB standard, improves the efficiency of the encoder on the basis of implementing functions and designs the FPGA.The paper firstly introduces DVB and DMB-TH standard, proposes the channel coding scheme for each standard and describes the design of LDPC encoder of DMB-TH standard in detail. Secondly, RS(Reed-Solomon) code is a important kind of linear block code and has very strong ability of correcting burst errors and random errors, so it is widely used in the field of error control especially in communication system. The outer code of the DVB standard's channel code is the shorten RS(204,188) code. The paper analyses the conception and arithmetic operations of Galois Field which is the basic mathematics theory of designing the encoder. Thirdly, in the process of designing the RS encoder, the paper puts forward two-level optimization of multiplication circuit and uses symmetric coefficients generator polynomial in order to greatly reduce hardware resource consumption. The development tool is Quartus II and the code is written in Verilog HDL language. The design is verified in APEX20KE FPGA of Altera Corporation. A testbench is established in which the input MPEG-2 TS is simulated and the output results are compared between the HDL model and C language coded model, so the function of the encoder is verified. Fourthly, the system adopts optimization of resource utilization, I/O timing, maximum clock frequency while designing FPGA. The compiler results prove that the system is a very efficient RS encoder, the frequency can reach to 157.43MHz. Finally, the modules of transport stream processing, energy diffusion, FIFO, convolution and interweaver are taken into account in this paper and the code is written in Verilog. The FPGA hardware resource consumption and the frequency of chips are available after compilation.The function and performance of the design meet the requirements through functional verification and comparison with the unoptimized system. The system is in accordance with DVB standard and implements the adequately utilization of FPGA hardware resource, it also reaches high clock frequency, so it is a high efficient and reliable channel coding system.