Design And FPGA Implementation Of Entropy Coding And Interpolation Part Based On AVS Standard

In the recent years,with the delelopment of digital technology,there is a revolutionary of restoration and disposal of video and audio signal,which translates analog signal into digital signal.But the digital signal information is too much.If you want to inprove the quality of image,the number will be gradually increasing.Thts is a great challenge of restroation and disposal of digital signal.In order to decrease the information,the compression of video signal came into being,which means using little information to show more image information signal.As in known to all,the desingation of a Encoder which can decrease information and retain the quality of image,has widely value of science and market.This paper propose a integrity of Encoder which can handle of image signal in the foundation of the introduction of modern video standard,such as MPEG-4,H.264/AVC,AVS,and gives a full introduction of the implement of the process of Entropy coding and Interpolation part of the Encoder,and uses Verilog HDL language to program it. At last,this paper use software and hardware environment to verify the two part of the Encoder by using Virtex 5 chips on line.The results shows that the two parts can handle of the image coding momently and can be downed into FPGA chips to handle of the certain operation.First,this paper introducts the modern standard of video,such as MPEG-4,H.264/AVC and AVS,and gives a introduction of the designation of the hardware framework,especially the Entropy coding and Interpolation part of the Encoder.Secondly,this paper translate the two part into Verilog HDL language,and use ISE environment to verify and simulate it.At last,the paper use FPGA chips tp verify it on line.The resualts displays that,the two parts can handle of the encoding of the image signal,and can be downloaded into FPGA chips to encode video signal.The innovation work of the paper has done includes:First,this paper studies the recent development of the video standard,especially AVS standard.And study the method of disposal of image signal based of AVS,especially the entropy coding and interpolation parts and the principal of them.Secondly,this paper study the recent development of FPGA chips,specially AVS standard,Virtes 5 chips and the operation of ISE and ModelSim SE environment and Verilog HDL language.Thirdly,based on the introduction of Entropy coding the Encoder,this paper proposes a method of detecting Exb-Golomb code's length in one clk by using two seletors links with the features of the FPGA chips.It is "first 1"detecting algorithm. And design a method of storing coding stream by tempories to handle of connection of the top data of macroblock and coding stream.This method not only increases the working speed of the Encoder,but deseaces the resources of the Encoder.Forthly,this paper optimizes the algorithm of the AVS standard,and proposes a framework of composation and padding of data,which means open up certain area to handle of the tempary data and increases the working speed.Espericially,it uses high order filter to interpolate the half and quarter pixels in one clk.It can handle of one line and one column pixels in one clk and decreases the time of calculation.This paper uses displacement and add algorithm to implace multiplication links with the features of the FPGA chips and increases the efficiency of the Encoder.Fifly,this paper design a FPGA framework using Verilog HDL language,and put it into simulation and synthesize and gives the results and data of the experiment.This paper puts the Encoder and Interpolation part language into Virtex 5 chips to verify.Choose one image,analyses it by rm52j to get the results first,and then compared with the results of the Vrites 5 chips on line to prove the correction and real-time of the design.