Design And Implementation Of Display Stream Compression Coding Circuit Based On FPGA

With the rapid development of multimedia technology,video image quality has been rapidly improved,especially the application of ultra-high definition video,which brings great challenges to the current limited transmission bandwidth.Compressing digital images is an effective measure to solve this problem.Display Stream Compression(DSC)is a low-cost,low-latency and visually lossless image compression standard for display links.It has high application value in the display part of embedded and mobile products,causing widespread concern.At present,the implementation of DSC encoding algorithm in hardware is one of the main research directions in the industry.This thesis designs a DSC encoding circuit and implements it using Field Programmable Gate Array(FPGA).Firstly,the algorithm and implementation process of color space conversion,prediction,quantization,reconstruction,Indexed Color History(ICH),entropy coding,flatness determination and rate control are analyzed in detail,and the commonly used acceleration schemes of FPGA are analyzed to provide theoretical basis for hardware implementation of DSC algorithm.Then the overall structure of the DSC encoding hardware circuit is designed.Four channels of the same coding circuit are used to calculate different slices in parallel,and the coding circuit adopts a three-stage pipeline structure.According to the different functions of the DSC coding algorithm,the coding circuit is divided into multiple modules and some modules are simplified.The module is designed.The Pmode module responsible for prediction and the ICH module responsible for finding the index value are used in parallel calculation.In the way,two different encoding methods for entropy coding are used in parallel processing to achieve the purpose of improving circuit throughput.Through the interface signal of each module of DSC encoding circuit and the data interaction within the module,each module is realized,and the data calculation among the modules is controlled by state machine.The coding circuit designed in this thesis uses the Modelsim tool to simulate the function of each module.By comparing the simulation results of the circuit with the output reference data of the C model,the correctness of the hardware circuit function design is verified.In the ISE14.7 development environment,the entire circuit RTL code is logically synthesized,and the corresponding timing and resource occupancy are given,and the test is performed on the Xilinx KC705 development board.The results show that the DSC coding circuit designed in this thesis meets the design requirements of 3:1 compression for 24-bit color image input test samples.The compression result is decompressed by software,after decompressing,the PSNR value of the image is above 30 dB.At 150 MHz working frequency,and about 31 frames of 1080 P images can be processed per second.The work of this thesis have reference value for hardware implementation of DSC algorithm.