Hardware Implement Of The Key Modules In Avs Encoder

AVS standard is the digital audio and video coding standard with independent intellectual property rights, formulated by Audio Video coding Standard Workgroup of China. Its performance is superior to MPEG2standard while is neck and neck with H.264standard. Currently, AVS decoder has possessed a mature development while AVS encoder, which is an important link in industry chain, is still waiting for a mature solution.AVS standard adopts a series of high computational techniques to achieve video coding of great efficiency; real-time coding enjoys huge data throughput. Its encoder is both compute-intensive and communication-intensive. FPGA platform possesses abundant register resources and logic resources, and the hardware implementation method of which is parallel processing can meet the design demands of numerous high-speed electronic circuits. This subject is aimed to develop cif-resolution real-time AVS encoder on Virtex-4platform.In this subject, a kind of one-way chip serial bus OCSB and the related unified algorithm module access protocol are designed, corresponding to the main features of Ethernet transmission abstracted. Based on this, on-chip network topology of algorithm module is proposed in this thesis. This structure consists of a main processing node and various algorithm modules IP cores that are connected to OCSB bus network through unified network interface UNI. The network includes two data passing channels and a state bus.With the fact that there exists a great deal of repetitive and regular high-density computation within video processing algorithm taken into account, these calculations are classified into different operations. The definition and description of data frame receiving and sending in each algorithm module of AVS basic profile have been completed. Additionally, FPGA design of sub-modules has been achieved according to the characteristics of algorithm.The FPGA design of DCT transform, quantization and IDCT transform, inverse quantization modules has been implemented based on Virtex-4platform. Quantization, inverse quantization and IDCT transform are merged into a pipeline unit for parallel processing, saving memory caused by storing intermediate data and improving coding speed.To improve coding speed, a kind of new filtering order of loop filter is proposed in this essay. The improved boundary filtering order maximumly reuses the data of current sub-module without affecting filtering effects, decreasing communication times between filtering module and the main processing unit.The method using RAM address hopping to achieve zigzag scanning is put forward; the efficiency of lookup is improved through reforming code table storage structure and inquiry mode. With the features of FPGA put into use, maximum parallel processing is achieved in sub-modules, improving coding speed.Using the FPGA development tool ISE10.1and ModelSim SE6.2b, the key modules of AVS based on FPGA can be implemented. According to simulation results, the design has high resource utilization and the maximum operating clock frequency is about118MHz. The design can be used in cif-resolution real-time AVS encoder.