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FPGA-based Wireless Communications System Design And Research

Posted on:2008-03-15Degree:MasterType:Thesis
Country:ChinaCandidate:W XieFull Text:PDF
GTID:2178360212991168Subject:Communication and Information System
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In the digital and information era , the digital IC applies extremely widely. Along with the development of micro electron technology and craft , the digital IC gradually develops from the electron tube, the transistor, the small scale integration electric circuit, the VLSIC to ASIC . However, the scope of ASIC's application is restricted by its long design cycle, large investment on its edition correction and its poor flexibility . The appearance of programmable logic devices has made up the ASIC's flaw, and makes it possible to design more flexible with smaller circuit size, lighter weight, lower cost and lower power consumption. The field programmable gate array (FPGA), developing from PAL, GAL, EPLD and other programmable devices , is as a semi-custom circuit of ASIC. It solved the lack of customization circuit, and also overcome the existing shortcomings of programmable gate circuit devices' s limited number.This paper was written about the way of using FPGA to design the processing of base band signal on a small unmanned aircraft system . All of the signal processing is designed by VHDL hardware description language, and simulated and debugged by Modelsim simulation system. Finally, the system is completed through programming to XC2S100, which is a FPGA chip produced by Xilinx company. All of the design has met the requirements of system.Firstly, in this paper we discussed about the to the overall structure of the base band signal processing design on a wireless communication system . Then, I gave a detail explanation of each module design principles and methodologies .Finally, we made a detail analysis of key technology and difficult. The most significant feature of this system is the use of FPGA design methods to achieve revised flexibility, small size, power dissipation. This system includes a digital phase-locked loop, error correction coding, the intertwined coding, adding scramble code, inserting Barker Code, frame synchronization identification, DPSK modulation and demodulation and the choosing of the whole timing. After all the components have been repeatedly modified and debugged, we achieved good results in the data processing., and the key difficult has been successfully solved. I has got simulating and real-testing result of the whole system.
Keywords/Search Tags:FPGA, Hamming codes, digital phase-locked loop, DPSK, Barker code, synchronization circuit
PDF Full Text Request
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