Research & Design Of Wireless Communication System Based On System On Programmable Chip

Nowadays, with the development of semiconductor technology, System on Programmable Chip, that is programmable SoC or SoPC, becomes more and more important. It has the flexible and programmable characters, moreover, it has many I/Os, its power consumption and cost is low.In this paper, I bring forward a new design way of Digital Phase-Locked Loop (DPLL) .At present time, the mainly design way of DPLL is to add or deduct pulse based on the characters of DPLL' s three departments strictly, thus DPLL occupies too much resource, at the same time, in order to meet the same phase-locked precision, it will spend more time to lock phase, according to these problems, this paper analyses the characters of the phase discrimination, digital filter and number controlled oscillator, uses high speed clock as sampling pointer, and designs the pointers of positive and negative level. By means of modifying the pointers, we can calculate the phase offset and lock the phase position. Because three departments of DPLL compose a whole, we can save the resource of system, and reduce time of locking phase, further more, in order to lock all kinds of signal phase conveniently, we can modify the DPLL' s program flexibly.In the meantime, the system includes not only the design.of DPLL, but also coding and decoding of error correction, block interleaving, inserting Barker code and disturb code, the design of frame synchronizer, the choice of the whole system timing sequence, and so on. I have modified and debugged the program of the system again and again, and have attained ideal data.