Research And Design Of FPGA-Base High-Order Phase-Locked Loop

There was a lot of problems to the receiver in the High dynamic environment of satellitecommunications, especially the contradiction between High dynamic performance and highsignal-to-noise ratio. We will increase the bandwidth of the tracking loop in order to improvethe dynamic performance of the receiver, but will reduce the signal-to-noise ratio. On thecontrary, improve the signal-to-noise ratio, will reduce the tracking loop bandwidth, lowerdynamic performance. It is very important to study how to reconcile the two. This paperintroduces how to design FLL assisted PLL’s high-level phase-locked loop to solve thisproblem.The paper focuses on the design of PLL loop filter. Taking the frequency ramp signal inthe satellite communication into account, we adopt the ideal type2loop filter design thirdorder PLL system. We introduce digital filter design methods in detail and analyzed the noiseperformance of the loop and dynamic tracking performance, given the detailed theory of loopnoise bandwidth derivation process, and create a complete loop parameters formula, appliedautomatically K-change module in Filtering loop K filtering sequence. For the phase-lockedloop high signal-to-noise ratio and high dynamic tracking capability, we designed anadjustable weight the second FLL auxiliary high-end third-order PLL phase-locked loop, inorder to improve the capacity of the phase-locked loop to capture high dynamic signal. Forthe problem of complex and the big structure in PLL loop filter algorithm, we propose theDigital filtering algorithm based on rectangular wave and the filter loop design. Thisalgorithm can reduce the implementation complexity and reduce the volume of the concretestructure, and having a good dynamic tracking performance in the high dynamic environment.Finally, the high-order phase-locked loop of the algorithm using VHDL language,Simulation through in QuartusII on analysis to verify the effectiveness of thealgorithm.Hardware debugging by FPGA development board, validation, and wait untilsatisfactory result.