Research On Design For Test Methodology For Core Based SOC Architecture

Currently, SOC design technology meets many challenges. The testability for SOC is one of main challenges, even the bottleneck of SOC design development. This dissertation mainly discusses the general test architectures of SOC and expands on three sub problems--Test wrapper design, Test Access Mechanism design and Test Scheduling.In SOC test, the I/O ports of IP core can not be accessed directly by the SOC's pins for the IP core embedded in the SOC. Therefore, test access mechanism which provides a channel from test resource to test sink is needed; test wrapper is an interface between TAM and IP core, which can control the IP core operating mode; scheduling is a process to determine the beginning and the end time of testing each IP core to minimize the total test time.This dissertation analyzes a P1500 test wrapper which is added to the I/O port for IP core using for isolating it form other cores. The design of test access mechanism is a chief architecture for SOC test which is used to transfer test data on the chip. And test bus is used extensively in TAM design. So the principle of test bus is analyzed and a general chip test architecture based on test bus named virtual TAM which can reduce the test time and test cost efficiently by matching the high-speed ATE channels to slower scan chains is presented in this dissertation. This architecture increases the width of internal test lines by adding a serial in parallel out register on the IP core's input and enhances the test parallelism by adding a parallel in serial out register on the IP core's output, so it can reduce the test time efficiently by increasing hardware overhead.Usually, there are many cores in a SOC. In order to reducing the total test time and total test cost, the TAM optimization and test scheduling should be done. And TAM optimization and test scheduling is a typical NP-complete problem. The linear programming model and rectangle packing method are discussed in this dissertation for SOC TAM optimization. Then a virtual TAM optimization method based on Lagrange multipliers which can work efficiently when the width of TAM is large to reducing the testing time and test cost is presented in the dissertation.