The Study Of Partial Scan Structure Of DFT In SoC

Design-for-test (DFT) in system-on-chip (SoC) can be classified to two categories: design of test structure in embedded cores and design of system test. The partial scan structure, which is the object of study in the paper, belongs to the former.Compared with the large overhead of area and performance in full scan structure, partial scan structure can get better effect. Considering the specialty of pseudo-random vector, a partial scan algorithm for BIST, which unifying the structure analysis and testability analysis, is presented in this paper. Then, the fault simulation experiments on ISCAS89 benchmark circuits by this algorithm is made, and the results, which made by the full scan algorithm and the partial scan algorithm only based on the structure analysis, is compared. The conclusion is achieved: for pseudo-random vector, compared with the full scan circuit and the circuit geted by partial scan algorithm only based on the structure analysis, the circuit geted by our partial scan algorithm can greatly reduce the test time with very close or even greater faults coverage and less area than the full scan.At last, the paper fulfills the partial scan structure in one SoC chip, Garfield. The partial scan algorithm is simplified in the case, and result shows that the simplified algorithm is good enough for the need of Garfield, that's to say, the operation of it is fast and easy, but it can also get good effect.