Simulation And Test For PDVQ Image Compression Chip

Image compression is always a critical technology in the image area and is also a hotspot in research area. With the development of multimedia and intranet, people are sincerely hoped to display much image information in limited bits number. According to this situation, this project team invents a real-time image-compression chip which base on PDVQ algorithm. This algorithm is a quick vector quantization arithmetic developed by the team member. Its RTL coding is written in Verilog HDL language, the chip was completed according to the major design flow of ASIC.This paper covers software simulation (adopted in 3 step—after RTL coding;after synthesis;after place and route) and hardware test.Through software simulation and hardware test,the correctness of the chip's function is verified.At first, Matlab is used to verify the circuit architecture and correctness of algorithm (behavior simulation) .Modelsim is also used to verify the correctness of the RTL coding through RTL simulation, and gate level netlist after synthesis is verified by pre-layout simulation, after post-layout simulation,the correctness of functional and timing after physical implementation are verified,and the highest frequency of clock in post-layout simulation is 100MHz.This characters meet the timing request at the start of design.The PDVQ chip is taped out by Charter in Singapore, which adopt 0.35μm COMS technique. Functional test is implemented on this chip in 2 ways, one is based on MCU with working frequency equals to 1 MHz, the other is based on FPGA with working frequency equals to 20 MHz.Finaly, based on the test results, it is clear that the chip's function is identify with the specification, and the chip can encode block image correctly.At last, this paper discussed an adaptive algorithm based on PDVQ which is developed by the project team. Here it is compared with PDVQ algorithm and prove itself to be practical. In this paper, firstly, the adaptive algorithm is acomplished in Verilog HDL; secondly,the coding is verified by simulation;finally,this design is implemented in FPGA use Quartus II 5.0.