Functional Test And Fault Test Data Compression On Digital Signal Processor IP Core

The rapid progress in micro-electroni technology promotes the adbent of System-on-a-chip (SOC), which brings integrate circuit into a new period of development. This progress make the TTM shorten, but also takes challeng to test. Because of the increasing of IP cores and expanding of the circuit size, testing data and time increase observably. The increasing test patterns and the increasing test time leads to higher cost. It is important to compress the test data in order to reduce the press of test.This paper is dedicated to test a 16 bits fix point DSP Core. Take software simulator as a golden reference, the instruction set test is successfully finished in three levels. Testing results illustrate that DSP core is fully compatible with the target instruction set. The design of SOC mainly adopts the technique of reusable intellectual-property (IP) cores, with the increase in the number of IP cores integrated, and its function becoming more complex (especially in DSP core IP), test data volume grows quickly. Test data compression becomes an important research direction. After the function test of the DSP core, this paper discusses a method for data compression, and designs the decode modules for the DSP core. After test on the curcirts of ISCAS-89, this methods is better than the standard FDR method.