Design Of PDVQ Based ASIC Chip And Code System

Because of the immense values of image compression, relevant research has always been the hot topic of image field. VQ(Vector Quantization) is a simple but efficient image algorithm with high CR(compression ratio), its CR is higher than traditional scalable methods. VQ algorithm is easy to implant in hardware, which can achieve very fast process speed, used in real-time image process applications. So VQ has become an interesting topic recent years.Based on traditional VQ algorithm, a fast PDVQ algorithm was developed, and its RTL code was wrote in Verilog HDL. This paper finishes the ASIC design of PDVQ chip according mainstream design flow.First, the verification and optimization work was done to make the RTL code synthesizable. To improve the testability, we design a DFT(Design For Test) for PDVQ chip. During this stage we used the Modelsim software by Mentor Graphics.Then proper constraints were set for PDVQ, and synthesis it using DesignCompiler by SYNOPSYS under Chartered 0.35um CMOS technology. The gate-level netlist was validated in Modelsim.Finally, Apollo was used to place and route the design. To conduct post-route simulation on Modelsim, the parasitic parameter was extracted by Star-RCXT of Avant!. PrimeTime used here to do STA(Static Timing Analysis). After DRC and LVS verification, the GDSII file was submit to foundry to tap out.PDVQ chip uses a global clock, which can run at 100MHz. For a medium complexity standard test image size of 512×512 pixel, the processing time is less than 20ms, it proves that PDVQ chip can compress about 50 frame image of such size per second. The area of PDVQ chip is 2.08×2.08 mm 2, dynamic power consumption is 242.26mW, and static power consumption is 66.64uW。Furthermore, this paper presents a compatible algorithm with higher CR, which can make full use of the redundant information of the image and reduce the computation. Conducted on 10 standard images, the experiment result shows that new algorithm can improve the CR by 25% average, while the PSNR only decreases 1.24% average. It can be implanted in FPGA to act as the front part of PDVQ chip, and then a complete and flexible codec system can derived.