Application Research Of SoftSerDes In Large Scale FPGA

The application of digital IC achieved broad development in the high-speed digital communications domain. FPGA succeeded to the advantage in large scale, dense integration and good dependability from ASIC. And FPGA abstained the disadvantage of long designing cycle, great investment and within an inch of alteration. FPGA will become the perfect choice step by step in the complex digital circuit design. The SERDES application to FPGA can implement a mass of data receiving and transmitting and can enhance the total of data flux. Compared with conventional SERDES, softSerDes has higher noise resistibility, low power consumption and easy upgrade to future product. Therefore softSerDes will have a wide foreground application in large scale FPGA design.Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew. The CDR technique need anolog Phase Locked Loop(PLL), which depressed some performance of the whole circuit. The article has presented a new and full digital design method, which has been designed and implemented basing on FPGA and called SoftSerdes. XILINX first advanced this technique ,and then ZTE adopt it firstly in the design of FPGA.In the article we implemented functional simulation of softSerDes at first. The result of simulation proved that this new technique can achieve prospective purpose. The article introduced correlative software used in the process of FPGA design. The article presented the design flow of FPGA, including simulation, synthesize, routing and test. The result of the test on circuit board proved that SoftSerdes can exactly achieve the transition of serial data to parallel data and have a good inverse proportion between performance and price.