A Research Of ΣΔ Modulator Based On Passive Filter Network

The circuit's implementation of theΣΔmodulator become a hot topic of the integrated circuits design in high speed developing digital and communication times, since it can reach a very high resolution in analog-to-digital convert. The research purpose of this thesis is to raise sample clock frequency to GHz in condition of low power.In this thesis, the theory of the single bit bit-stream generated byΣΔmodulator was introduced first. Although only 1 bit quantizer (comparator) is used in the modulator, a very high resolution can still be reached by the over-sampling and noise-shaping techniques. Furthermore, this thesis has make a analysis of first-order, second-order and high orderΣΔmodulators, the systems which are above third-order would be unstable although they can reach pretty good noise-shaping performance.Nowadays most of theΣΔmodulators, including discrete-time and continuous-time structure, are all based on active integrators. The performance of the classicalΣΔmodulators built with active integrator will be affected by the operational amplifier seriously, and it is difficult to process the wide-band signal. A wide-bandΣΔmodulator based on the passive filter network was put forward in this thesis. The task of active integrator is achieved by passive filter network in this kind ofΣΔmodulator, whose performance will not be affected by the operational amplifier. Therefore, the bandwidth of signal that can be processed has become much wider.The theory of this kind ofΣΔmodulator based on passive filter network has been given in this thesis. By a detailed analysis of first-order, second-order and high-order systems, this thesis has given two circuit designs which are based on RLC and RC filter network system finally. The system and circuit simulation results have been given in this thesis. The simulation indicated that the band-width can be broadened to be 10MHz, and the Dynamic Range can reach 44dB and 45.5dB respectively. The layout of the circuit was designed with TSMC 0.18um CMOS technology, and the power of two chips is 27mW and 23.4mW respectively when the power supply is 1.8V. The performance has improved awfully compared to traditional modulator (sample clock frequency is 100MHz and power is above 50mW).Besides the completed system test, we tested some circuit module in the system by disconnecting feedback loop during the test process of chips. The result of test is not so good compared to the result of circuit simulation. This thesis has given a detailed analysis of circuits test results in the system. Some means that maybe improve the performance of this system has also been given in this thesis.