Key Technologies In Signal Processing Research And Implementation For MC-QAM Modulator

In this thesis, by introducing the application background of digital TV modulator, we have analyzed the implementation structure of Multi-Carrier QAM (MC-QAM) modulation technology. Based on the analysis and remark of status, most departments of modulator are optimized. And at the same time, the following problems are mainly considered:Coefficient compressed structure for implementing various FIR filters is presented. Because of different coefficients of the digital FIR filter having greatly different absolute values, by using floating numeric theory for reference, this method modifies the accumulator's alignment and compresses the coefficient's bitwidth to increase the equivalent quantization bitwidth of pre-storage quantized coefficients. Neither increasing the hardware quantization bitwidth nor the filter orders, coefficient compression method could improve the quantized FIR filter's actual stopband performance 10~20dB. On this basis, the stopband attenuation could be further improved about 3dB by slightly modifying the overall filter gain. The parallel, serial and mixed structures for different device realization are respectively introduced in this thesis.The causation of stopband performance degradation for Arbitrary digital signals Sampling Rate Conversion (ASRC) has been analyzed, and its implementation structure optimizing method has also been suggested. According to the status of lacking researching in prestored ASRC filter, the proposed algorithm divides this filtering process into two steps: integral interpolation and fractional decimation. Detailed analysis of the rudimental noise in integral interpolation and rudimental noise accumulation in fractional decimation, are presented. The relationship between the interpolation factor and the rudimental spectrum has also been corrected. With the upwards coefficient compression algorithm, the performance of the bitwidth-limited ASRC filter could be ameliorated. And because of the coefficient symmetry in prototype filter, we could reduce the consumption of the storage to its half by memory decomposition and address turnover. Only few coefficients memory usage could bring the advantage of exponential multipliers and adders'decreasing. The result shows that only with this simple structure, the purpose to replace the complicated Farrow real-time computing SRC filter could be achieved.A novel architecture optimization technique for halfband filter has been proposed. Because of the characteristic that half of halfband filter's coefficients are zeros, factoring out a desensitized pre-filter from it could significantly reduce the coefficient sensitivity, and decrease the requirement of quantization bitwidth, for the purpose of implementation optimization and multipliers reduction. On this basis, the serial filter designing method by multiplier time division multiplexing, and the cascade of two or more halfband filters for multistage interpolation, are both effective in logic resource reduction. Comparing with the traditional multiphase filter, this method decreases the number of multipliers to its one eighth, while not degrading the filter performance.A method of high-order CIC compensation filter is given. Aiming at the main lobe droop in the desired passband, we present a method that compensate CIC filter with a high-order filter based on the traditional second-order compensation and sharpening technique. Optimal Chebyshev approximation is introduced into the design of CIC and its compensation filter. This improvement makes their cascades be turned into an optimal equiripple filter, and this makes wideband CIC image rejection filter design become possible. The result indicates that one stage increasing of the compensation filter could decrease magnitude order of the passband ripple.A multi-carrier QAM model modification and implementation has been introduced. In view of the limitation that multi-carrier superposition could only be completed in the intermediate frequency band, we present the base-band mixing architecture and deduce its algorithm in detail. In traditional scheme high frequency carrier must be synthesized before mixing, but in new method only the frequency offset carrier is need to be generated, which is comparable with the bandwidth of the signal. And the differences and similarities of the situations of odd and even carriers have also been discussed. Considering the characteristics of the base-band mixing algorithm, we give its final optimized logic structure.A novel non-phase truncation error DDS design method has been described. Based on analyzing the source of this error, combining with the DDS hardware structure, we modify the DDS accumulator's phase step in arithmetic to eliminate the truncation error. Only with slightly modification in logic, the interference in frequency band from phase truncation has been completely removed. It has the advantage that the performance improvement could be achieved by linear increasing the coefficient memorizer for higher quantization precision, but no longer need to increase memorizer in exponential for less phase truncation error. By this method our DDS's SFDR improved by more than 17dBc. Furthermore, time division multiplexing with the look-up table, storaging in differential amplitude could economize the memory by 2 bits. And the method of amplitude jitter could further suppress the noise plane near to the carrier by 10dB to obtain better frequency synthesizer performance.In conclusion, we test the actual performance of the high density MC-QAM modulator, and compare it with the traditional equipment. Based on the 30% logic resource consumption economization, the performance index of MER has been improved by 5.5dB, while all the function requirements have been achieved. At last, the further development directions of MC-QAM modulator have been proposed.