Research For Signal Integrity In Deep Submicron IC Physical Design

With the constant shrinking of character size, the era of deep submicron (DSM) and ultra deep submicron (UDSM) has come for the IC industry. Along with the ever growing of chip function, signal integrity has now become the key problem and consideration in the physical design of deep submicron IC.Signal integrality is the status that the signal is not losing. It is a function character that figures the signal is remain correct after the transmission. There are there factors which influencing the Convergence of Signal integrality in the bad hand. They are crosstalk, IR-drop and electro migration. Which influenced most is crosstalk. Crosstalk noise caused by coupling capacitance will result in a grate deal of timing violation and logical error. IR-drop and electro migration can also reduce the chip performance and even make the chip out of work.This paper made attention to research the physical design flow which is based on Signal integraty problem mostly including crosstalk control flow, IR-drop analysis, and electro migration analysis. After we analyzed the factors which influence the crosstalk and the crosstalk noise themselves interrelations, by the experiment, we give several advices which can control the crosstalk effectively. Based on the result in front, we expatiated that integrated crosstalk control flow should has three parts, they are crosstalk prevention, PrimeTime SI static timing analysis based on crosstalk and the crosstalk fix flow of PrimeTime SI-Astro. We also validated this crosstalk control flow is effective by experiment. Analysis of IR-drop and electro migration will greatly instruct the design of power supply network and the layout of the signal line. Associate with the research item of Garfiled SoC in our engineering center, we found if we affiliate our signal integrity control flow into the physical design flow, the out of line designs caused by the signal integrity problem reduce a great deal. In this experiment, the amount of violative path is been cut down 60%. Reduce the times of the iteration from 8 to 3, may accelerate timing closure. Improving the design of power network and routing based on the analysis of IR-drop and electro migration,can finally eliminate serious IR-drop existing in the chip.This paper successfully transfers the process from 0.25μm to 0.18μm ,and remove the influenence of the signal integrity.It makes the main frequency arise to 100MHz and meets our goal.