The Physical Design Of "Costar" DSP And Solution Of Signal Integrity

First of all, this paper introduces the development history and research condition of semiconductor process technology and IC design methods all over the world. From the fact of difference in the development of integrate circuits industry between our country and advanced countries in the world, one of critical issues that must be solved to develop 1C industry is proposed. That's to solve deep sub-micro effects such as interconnect delay and signal integrity issues which are caused by smaller feature dimension and bigger chip size in deep sub-micro VLSI design.This paper analyzes the impacts of interconnect delay on the circuits and corresponding influencing factors, aiming at interconnect delay and signal integrity problems occurring in very deep sub-micro VLSI. Interconnect modeling and parasitic parameters extracting are also analyzed. Then the causes of signal integrity occurring and its content are investigated. And material measures to solve signal integrity issues and to optimize interconnect delay are also proposed. Then these measures are successfully applied in the physical design of a kind of high performance, embedded and general-purpose DSP chip. The physical design of the DSP chip has been finished and all verifications have been done successfully according to the preconcerted targets. Now the DSP chip has been taped out already. The very deep sub-micro physical design flow adopted in this paper includes: floorplan, advance placement and routing, timing and congestion-driven placement, clock tree synthesis, placement optimization, routing, circuit verification, and etc.The major contributions of this paper include: 1) It builds up a suit of design flow applicable in very deep sub-micro ICs of 0.18 m and below, which combines logic synthesis with placement. 2) It analyzes and solves the signal integrity issues in very deep sub-micro ICs of 0.18m and below.The design flow and its solutions of signal integrity proposed in this paper can be applicable in high-speed very large chip design of 0.18 m and below.