Signal integrity for SOC design and verification

System on Chip designs combine digital and analog blocks built over a common substrate and share same interconnects. Designing such systems is becoming increasingly difficult because of crosstalk coupling between interconnects, capacitive coupling in substrate and higher level of power dissipation throughout the chip.; This research discusses signal integrity issues such as substrate noise, crosstalk and IR drop that are primary concern in today's SoC design. Signal integrity issues have become more dominant and challenging as our technologies progress toward deep-submicron technologies.; This research investigates signal integrity issues and analyzes them using Cadence software tools. A 32-bit Pseudo-Random Number Generator is used as an SoC model. This research presents design techniques that are used to improve the performance and functionality of the design under signal integrity influence. The accurate modeling of substrate noise, crosstalk and IR drop is an important step for verification of SoC systems. This research addresses signal integrity problems by applying design techniques based on simulation reports obtained from Cadence software tools. PacifIC, SeismIC and VoltageStorm are used to analyze crosstalk, substrate noise, IR drop and electromigration, respectively.