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Design Of A11-bit80MSPS Segmented Current Steering DAC

Posted on:2014-02-13Degree:MasterType:Thesis
Country:ChinaCandidate:Y L PuFull Text:PDF
GTID:2268330401465847Subject:Electronic materials and components
Abstract/Summary:PDF Full Text Request
Along with the fast-speed development of communication, computer andmultimedia digital technology, digital information has gone deep into every aspect ofpeople’s lives and work. However, we need the analog information which can bevisually felt or observed at most time, so their conversion is necessary. As the core, theimportance of the DAC is obvious. It will certainly get more and more attention of ICdesigners. CMOS DAC based the SoC is to become one of the most challenging ICdesign issues because of area and power consumption requirements.This thesis designs a segmented current steering DAC with an11bit resolution and80MSPS sampling rate which is based on the SMIC0.13μm1P6M CMOS process. Ithas I/Q dual channel and applied to the analog front-end in wireless communicationSoC, producing a5mA full-scale output current and using a "6+5" segmented structureunder dual power supply (3.3V/1.2V), the area and power consumption is960*740μm~2and60mW. In analog part, the current source mirrors the reference current provided bythe bandgap uses a PMOS cascode structure to increase impedance. Differential switchensures that the current path always exists. Pseudo transistor is connected to the outputport for reducing the clock feedthrough effect. In digital part, the decoder uses ranksdecoding, two3-7decoders become one6-63decoder. The latch also has the role of theswitch driver when reduces the cross point of switch signal. The design idea of smallersize and lower power consumption but meeting requirements is the same as thecommercial analog IP design patterns.Cadence Spectre, Hspice and Matlab are used for the circuit design and simulation;Cadence Virtuoso and Calibre play the role of design and verification of the layout. ThisDAC has been fabricated by MPW process. The measured results show that the INL andDNL is±0.5LSB and±0.3LSB, the SFDR is58dB and54dB when inputting1MHz and10MHz signal, which can prove the DAC chip, designed in this paper can meet therequirements of applications in wireless communication.
Keywords/Search Tags:DAC, Current Steering, CMOS, SFDR
PDF Full Text Request
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