The Design Of An Asynchronous Structured Data Flow Processor

With the chip integration and workload growth, the circuit design requirement of speed and power becomes more and more strict. Hence, the global clock-based synchronous circuit design method is facing big challenge as its congenital defects of the clock. At the same time, asynchronous circuit design owing a serie of advantages such as low-power, high-performance, makes itself the focus of research.In this paper, data flow processor is researched as the main object,this paper analyzed the asynchronous design method. And applied the asynchronous mapping method to separate the control structure and data structure; by the replacement of the structure cell with asynchronous new one, it replaced the control structure with global clock and meanwhile maintained the functional structure of pipeline. In this way, it proposed the structure of asynchronous pipelined data flow processor, to achieve the main purpose of reducing its power.Based on the design ideas above, the main innovation and contribution of this paper are as follows:1.In this paper, it summarized the asynchronous design method based on asynchronous mapping.2.Based on the asynchronous mapping design method, this paper proposed the improved self-controlled cell applied in the asynchronous mapping of data flow processor; the cell also fulfilled the function of asynchronous control structure and 4 phase handshaking protocol.3.Consided by the structural characters of data flow processor, it put forward a 2 level cycled fork-join pipelined asynchronous structure, and it applied the improved self-controlled cell with sequential modules, and realized the system of asychornous data flow processor...