The Research Of The Realization Of 10bit Pipelined Anolog To Digital Converter

System-on-a-Chip (SoC) requires the integration of analog circuits and digital circuits on a single chip. Technology compliable, performance optimized A/D converter(ADC: Anolog to Digital Converters)is an important building block as the bridge of the analog world to the digital section in SoC.It is important and necessary to research ADC with high speed,high resolution,low power dissipation by adopting standard CMOS process. The pipelined ADC can achieve high speed and high resolution. Further more, the number of comparators have been decreased, so the area is decreased. It introduced in this paper a 10bit,3.3V,33MHz sampled pipelined ADC. The key cells of ADC have been simulated in tsmc 0.35μm process by HSPICE environment.The pipelined ADC has many advantages. It can work at high speed, achieve more than 8 bit high resolutions, reduce the quantity of comparators and so on, so it can decrease the areas and reduce the power dissipation. It introduced in this paper a pipelined CMOS ADC. This paper have done work follows:(1)Based on traditional 1.5bit/ stage pipelined ADC , make the design more blocking by optimize the system module. The first nine stages of the system have been improved by using the same architecture,the tenth stage need only one comparator ,and the comparator needn't high precision, but can do digital correction to the ninth stage. It reduced the difficulties of the circuit design, also saved the design time. And simulated in Matlab/simulink environment.(2) Analyze and research some core cell circuit: the sample-and-hold circuit, SubADC, SubDAC and so on. The key cells of ADC have been simulated in tsmc 0.35um process by HSPICE environment. This paper introduced a dynamic comparator, it can enhance the speed, reduce the power dissipation, and the direct current power dissipation of the dynamic comparator is zero. (3)Analyze some system errors. The main errors are gain errors, SubADC errors, SubDAC errors. This paper analyzed these errors. And applied gain error correct technology and comparator digital correct technology to the architecture.