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Research And Development Of The CPPLL And Its IP Core Realization

Posted on:2007-02-20Degree:MasterType:Thesis
Country:ChinaCandidate:G F YouFull Text:PDF
GTID:2178360215470322Subject:Software engineering
Abstract/Summary:PDF Full Text Request
The higher the clock frequency is, the more PLL(Phase-Locked Loop) influences the performance of the microprocessors. Phase-Locked has been one of the core technique in modern microprocessor. The CPPLL(Charge-Pump PLL) has been used widely because of the merit of integrated easily, low power, low jitter and no phase difference locked. This thesis has designed a high-performance and low noise CPPLL for the high performance JX- microprocessor.This thesis studied the theory of third-order CPPLL, proposed the optimization method, and realized a third-order CPPLL for the JX high-performance microprocessor. The results of the verification and testing proved that the CPPLL was stable, low power, low jitter and no phase difference locked.This thesis discussed and solved the following problems:1) Optimized the PFD(Phase and Frequency Detector) to reduce the Dead-zone;2) Adopted a new type CP with voltage control amplifier, solved over-charge and depressed the effect of charge sharing;3) Adopted a second-order RC filter to reduce the output ripple, and optimized the parameters of the filter;4) Adopted the improved difference symmetry load structure oscillator, designed the bias voltage circuit and same swing output circuit, reduced the noise of VCO (Voltage Controlled Oscillator);5) Added losed-lock detect circuit to improve the stability of the PLL. This thesis adopted SMIC 0.18um CMOS process, realized the third-order CPPLL, and the area of the chip is only 910um×178um. Under the condition that the noise swing on the 1.8V power line in the PLL is about 350mV ,the testing result of the chip indicated the Pk-Pk value of cycle to cycle is 319.5ps. Now the PLL has been used in the JX-microprocessor successfully, and the highest stable output frequency reaches to 600MHz.Finally, this thesis designed the IP core of the CPPLL, created the Verilog function model, the physics model and the timing dissipation model, discussed the test model, and described the deliver information.
Keywords/Search Tags:Phase-Locked Loop(PLL), Charge-Pump(CP), Phase Niose, Jitter, Intellectual Property Core(IP Core), View
PDF Full Text Request
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