The Design Of CMOS Rfic Power Amplifier

The basic units of the satellite were made of lump components in the past. In nowadays, because of the development in micro-electronics and micro-mechanism fields, the satellite is becoming more and more small. The"General Cell"which made in a SoC is a basic unit of the aeronautical satellite. After analyzing the demands of downlink communication system of the"General Cell", the thesis came up with a design of RFIC power amplifier according to the requirements of the system and validated this scheme to be feasibility by simulation.The Bluetooth chip nRF2401 uses the GFSK modulation. After analyzing and comparing the characteristic of every class power amplifiers, the thesis bring up with the idea of using a switched mode power amplifier to achieve the demanding output power and the higher efficiency.As all known, the design of the power amplifier is still the bottleneck in RFIC design because of the characteristic of the CMOS technology. The thesis research the CMOS technique limitation in the PA design and came up with the resolve scheme.The power amplifier which designed in this thesis used the differential two-stage structure. The drive stage is made up of cascode class-F topology. A"big"MOSFET is used in the class-E output stage. The thesis did the simulation of the PA by ADS with the TSMC 0.18μm RF CMOS model, and completed the layout of the PA. According to the simulation results, the CMOS RFIC PA we designed works steadily, the output power is 24.3dBm and the PAE is 58.1%, so the PA can be used in the communication system of the"General Cell".In the end of the thesis, we came up with a measure of the ideal inverse class-F PA design which shows a way to design RFIC PA in the future.