.2.45 Ghz, Low Noise Amplifier Design Of The Cmos Process

This thesis realizes the LNA based on CMOS technology, which is the key block in receiver's front-end. Firstly, LNA is the first stage in a tipical wireless receiver. Secondly, LNA must provide big enough power gain in order to depress the noise figure from back stages. Thirdly, as to the high integrated SoC, LNA should have lower power consumption. Fourthly, when big signal comes, LNA should cause small distortion, which means LNA should have high enough linearity. Finally, LNA must look 50 input resistances in to the input source. It is important to trade off these parameters and optimize the entire performance. That's also is the key point to the LNA design.This thesis is based on the project—receiver chip on 2.45GHz, the author was responsible for the LNA block. A fully integrated narrow-band LNA at 2.45GHz for WLAN application was implemented in JAZZ 0.35μm technology with Cadence IC 5.0 design kits. The layout of LNA with ESD-protected is also designed. The result is near international level. Besides, a comparison between CMOS LNA and BJT LNA in TSMC 0.35μm technology with cascode inductive degeneration was made. Conclusions are made on that. For the engineer development needs, this paper discussed LNA's designation, simulation and test. Mainly it includes:1. Analysis and comparation is made between the different system topoloties in order to fulfill the WLAN application in SoC design.2. RFIC basically indexes and componets models are analysed, especially the MOSFET, because of its key role to the whole circuit design.3. Based on the four topologies's entire performance for 2.45GHz LNA anlysed, the cascode topology is adopted for the circuit design finally. The cascode noise model, noise analysis and optimization are done.A fully integrated 2.45GHz LNA circuit is designed. The temperature and technical warp analyses are done, and test precept is brought forward. Besides, LNAs in CMOS and Bipolar technology are analysised.